Use this page to discuss script 4067 automatic generator for Verilog HDL (upgraded) and RtlTree

  • Add constructive comments, bug reports, or discuss improvements (see the guideline).
  • Do not document the script here (the author should do that on
  • This page may be out of date: check the script's page above, and its release notes.


Suggest to add auto end comment function like in Emacx. That is, add an end comment for each if-else block after the "end", like "else // if !(a & b)", "end // if (a & b)". --February 25, 2014

Rtl Tree is limited to only the folder where files are. The sub modules are unresolved. When we move to sub folder we can go through sub module and modules within it. -- February 26, 2018