Wikia

Vim Tips Wiki

Script:4067

Talk0
1,612pages on
this wiki
Revision as of 05:24, February 26, 2014 by JohnBeckett (Talk | contribs)

(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)

Use this page to discuss script 4067 automatic generator for Verilog HDL (upgraded) and RtlTree

  • Add constructive comments, bug reports, or discuss improvements (see the guideline).
  • Do not document the script here (the author should do that on vim.org).
  • This page may be out of date: check the script's vim.org page above, and its release notes.

CommentsEdit

Suggest to add auto end comment function like in Emacx. That is, add an end comment for each if-else block after the "end", like "else // if !(a & b)", "end // if (a & b)". --February 25, 2014

Around Wikia's network

Random Wiki