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Use this page to discuss script 4743 systemverilog: indent script for Verilog and SystemVerilog

  • Add constructive comments, bug reports, or discuss improvements (see the guideline).
  • Do not document the script here (the author should do that on
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Adding ) causes a reindent while editing code. Fixing with ( should also reindent to put back in place. -- Fixed in 0.5

Behavior is unpleasant b/c inline editing causes spurious shifting. For example:

   a = (b || c);

Now go back and edit line 2 by expanding 'c' into '(c || d)'. If you start from the end first by adding the extra parenthesis first (')'), then the line will shift left. This is annoying. It will fix itself when the extra right parenthesis ('(') is added. This problem could be fixed by differentiating which indent openers and closers are used. For example, if the indentation is caused by 'begin', then only 'end' should bring the indent back.

>> Syntax Highlight uvm_info,uvm_error,etc do not highlight. Also $display/psprintf/sformatf system tasks do not highglight.

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